NIFTY routing for LArPix

LArPix is an existing pixelated readout chip for liquid argon time-projection chambers, with many channels each connected to a pixelated electrode. Unlike the 4D Pixel work, networking in LArPix happens chip-to-chip rather than pixel-to-pixel: chips are wired into an off-chip 2D mesh, one tile at a time (10×16 chips), with only vertical and horizontal links — no diagonal connections. Each chip’s Hydra I/O interface already routes packets between four cardinal ports (North, South, East, West), sorting traffic into upstream data, downstream data, config read/write, and message buffers, and a state machine decides what to capture, process, and forward.

To bring NIFTY’s adaptive routing to this platform, the project is developing a new chip revision — informally called vN1, since it now deviates from the production LArPix design — on a 180nm CMOS process. The smaller node gives access to cheaper, more frequent multi-project wafer runs while still working with existing LArPix testing infrastructure. The redesign adds a dedicated NIFTY message path alongside the existing upstream/downstream/config buffers on both the receive and transmit sides, and makes the downstream port connections configurable rather than fixed. The goal is for each chip to share live status from its data and config buffers with its neighbors, so nodes can sense where congestion is building up and selectively drop or reroute packets — the same fault-tolerant, congestion-aware philosophy explored in the Simulation tool, applied to LArPix’s real chip-to-chip network.

The vN1 design is targeted for verification readiness by mid-September and chip submission in mid-November 2026.