NIFTY routing for 4D Pixel detectors

4D Fabric is a joint effort to design a single 28nm CMOS pixel readout chip, PixCanvas, that combines three otherwise separate lines of R&D: precision timing from the ECRP program (the “4D” in 4D Fabric — adding a time dimension to standard 3D hit position), the intelligent, fault-tolerant on-chip mesh networking developed under NIFTY, and CMOS+X post-processing that lets the same die be paired with novel thin-film sensor materials. Rather than pursuing three separate prototype chips, 4D Fabric merges their requirements into one readout ASIC.

Conventional pixel readout chips like RD53 stream hits out through fixed, column-based readout paths — efficient, but vulnerable to congestion and to single points of failure. PixCanvas instead routes hits across a reconfigurable mesh of cores, using the same adaptive, congestion-aware routing strategies developed for NIFTY. Early design decisions — mesh topology, router logic, core layout — have been explored using the same simVis toy-simulation tool featured on the Simulation page of this site. Those studies show that denser topologies such as hexagonal and octagonal meshes hold up far better under node failures than a simple 2D mesh, keeping latency low and delivery success high even with a significant fraction of cores disabled.

The chip is being built with a standard digital-on-top ASIC design flow, with RTL for the core and router currently in progress. PixCanvas is targeted for submission on a 28nm shuttle run in November 2026.