About NIFTY
As particle physics sensor arrays grow larger and more complex, single point failures become a major obstacle to scaling detectors further. Sensors can fail from manufacturing defects, or be damaged in real time by radiation and cryogenic operation. NIFTY (Network Intelligence and Fault Tolerance) is developing artificial intelligence for the on-chip communication networks that read out these sensors, so that detector systems can tolerate failures without external intervention while also balancing data load for lower power and higher bandwidth.
The project builds on Hydra I/O, a fault-tolerant ASIC network developed at Berkeley Lab for the DUNE Near Detector, which lets a mesh of chips route around failed neighbors without compromising the rest of the network. Hydra’s reconfiguration logic today lives off-detector, in software that monitors the system from the outside. NIFTY aims to bring that intelligence onto the chip itself, so each node in the network can sense faults and rebalance traffic in real time.
Two state-of-the-art readout architectures anchor the work: the Hydra communication network used by DUNE, and the RD53 pixel readout chip developed for the ATLAS and CMS experiments at the LHC. Both currently rely on static, pre-configured routing. NIFTY is developing an intelligent version of Hydra with real-time, adaptive routing, and extending the same ideas to new architectures — including 3D networks for wireless “smart dust” sensor arrays and in-pixel neural processing that could add fault tolerance, load balancing, and data compression directly within a chip’s pixel matrix.
The project combines integrated circuit design, machine learning, and particle physics instrumentation expertise across Berkeley Lab, UC Irvine, and the University of Texas Arlington. The interactive Simulation on this site lets you explore how different routing strategies and network layouts hold up under sensor failures and congestion.
This work is funded by the Department of Energy, Office of High Energy Physics.
NIFTY routing for 4D Pixel detectors
NIFTY routing for 4D Pixel detectors
4D Fabric is a joint effort to design a single 28nm CMOS pixel readout chip, PixCanvas, that combines three otherwise separate lines of R&D: precision timing from the ECRP program (the “4D” in 4D Fabric — adding a time dimension to standard 3D hit position), the intelligent, fault-tolerant on-chip mesh networking developed under NIFTY, and CMOS+X post-processing that lets the same die be paired with novel thin-film sensor materials. Rather than pursuing three separate prototype chips, 4D Fabric merges their requirements into one readout ASIC.
NIFTY routing for LArPix
NIFTY routing for LArPix
LArPix is an existing pixelated readout chip for liquid argon time-projection chambers, with many channels each connected to a pixelated electrode. Unlike the 4D Pixel work, networking in LArPix happens chip-to-chip rather than pixel-to-pixel: chips are wired into an off-chip 2D mesh, one tile at a time (10×16 chips), with only vertical and horizontal links — no diagonal connections. Each chip’s Hydra I/O interface already routes packets between four cardinal ports (North, South, East, West), sorting traffic into upstream data, downstream data, config read/write, and message buffers, and a state machine decides what to capture, process, and forward.
NIFTY routing with Spiking Neural Networks
NIFTY routing with SNNs
Most of the routing strategies explored elsewhere on this site — greedy shortest-path, congestion avoidance, token passing — are hand-written, deterministic algorithms. NIFTY is also investigating a more ambitious alternative: using a Spiking Neural Network (SNN) as the decision-making core of the router itself, so that each node’s routing choices come from a small trained model rather than a fixed set of rules. This is meant to make individual chips genuinely intelligent — able to recognize and adapt to traffic and failure patterns that a linear algorithm wasn’t explicitly designed to handle — without the power cost that normally comes with running machine learning inference on-chip.